InGaAs linear sensor reference circuit design - Section 9

John Gilmore, Lu Cheng, Hamamatsu Corporation
Scott Hunt, Analog Devices, Inc.
December 15, 2018

This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.

Section 9: Test Results

9A. Timing Operations and Analog I/O Signals

This is the timing diagram of the G9201~8 and G9211~4 sensors. The integration time is set by the Reset input pulse width. Each pixel is being read out every 8 clocks.

Figure 9-1: The G920x sensor timing diagram

In the software interface, the pixel format, readout mode, integration time, temperature, bias voltages, and the number of line data to be written can be defined.

Figure 9-2: Parameter setting in the software interface

Pixel Number Select: 256 or 512.

For a 512-pixel array, there are two video output ports on the sensor chip: even and odd. Three readout modes are designed to read out from the sensor depending on the different multiplexer timing:
Multiplexer Timing (1) – Even/Odd simultaneous (parallel)
Multiplexer Timing (1a) – Non-Return to Zero (stagger)
Multiplexer Timing (2) – Clock burst with return to zero between pixel reads (bursts) – the same as C8062, the standard InGaAs multichannel detector head offered by Hamamatsu

The three different timing modes are tested, and the timing diagrams and test results are shown in Figures 9-3 to 9-18.

Figure 9-3: Timing diagram of MUX Timing (1) - Parallel clocking

Figure 9-4: Test results of CLK and AD_Trig signals at MUX Timing (1)

Figure 9-5: Test results of video output signal at MUX Timing (1)

Figure 9-6: Test results of Even/Odd SEL and video output signals at MUX Timing (1)

Figure 9-7: Test results of AD_CONV and video output signals at MUX Timing (1)

Figure 9-8: Timing diagram of MUX Timing (1a)

Figure 9-9: Test results of CLK and AD_Trig signals at MUX Timing (1a)

Figure 9-10: Test results of AD_CONV and video signals at MUX Timing (1a)

Figure 9-11: Test results of CLK and MUX output signals at MUX Timing (1a)

Figure 9-12: Test results of CLK, AD_Trig and video output signals at MUX Timing (1a)

Figure 9-13: Timing diagram of MUX Timing (2)

Figure 9-14: Test results of CLK and AD_Trig signals at MUX Timing (2)

Figure 9-15: Test results of Even/Odd SEL and video output signals at MUX Timing (2)

Figure 9-16: Zoom-out view of Figure 9-15

Figure 9-17: Test results of AD_CONV and video output signals at MUX Timing (2)

Figure 9-18: Zoom-in view of Figure 9-17

9B. Dark Stability

To verify the dark output is stable over time, indicating the InGaAs sensor cold-side temperature is stable at 0 deg. C., 600 scans are collected at 1 second integration time in the dark and the standard deviation is calculated for each pixel. Note: The level grouping is caused by Even/Odd CMOS ROIC variation. This is normal Even/Odd output pattern.