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InGaAs linear sensor reference circuit design - Section 5
John Gilmore, Lu Cheng, Hamamatsu Corporation
Scott Hunt, Analog Devices, Inc.
December 15, 2018
Section 1: Introduction
Section 2: System description
Section 3: Analog devices sensor board
Section 4: FPGA/USB processor data path
Section 5: FPGA/USB processor control/status path
Section 6: FPGA design description
Section 7: USB sub-system
Section 8: PC software and IGAA driver library
Section 9: Test results
This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.
Section 5: FPGA/USB Processor Control/Status Path
- Table 5-1 Control Path I/O Configuration
-
CYUSB3014-BZX Pin
Synchronous Slave FIFO Interface with 16-bit Data Bus
Interconnect Board
Net NameFPGA Pin
EZ-USB PWB
I/O VoltageDescription
Name
Location
Control/Status Path
I2C_GPIO[58] D9 I2C_SCL USB_SCL L13 VIO5 SCL line of the I2C control bus
Note: Jumper on interconnect board from
J3.88 to J2.132 neededI2C_GPIO[59] D10 I2C_SDA USB_SDA M14 VIO5 SDA line of the I2C control bus
Note: Jumper on interconnect board from
J3.86 to J2.134 needed
5A. Access Protocol
- The FPGA acts as I2C slave with address 0xAA.
- EZ-USB FX3 processor acts as an I2C master.
- Each I2C write transfer consists of the following:
- START (generated by master)
- Byte 1 = 0xAA
- ACK (generated by the slave)
- Byte 2 = Selected control register address
- ACK (generated by the slave)
- Byte 3 = Data byte to be written to the selected FPGA control register address
- ACK (generated by the slave)
- STOP
- Each single byte I2C read transfer consists of the following:
- START
- Byte 1 = 0xAA
- ACK (generated by the slave)
- Byte 2 = Selected control register address
- ACK (generated by the slave)
- RESTART
- Byte 3 = 0xAB
- ACK (generated by the slave)
- Byte 4 = Data byte from the selected control register returned by the FPGA
- NACK (generated by the master)
- STOP
- Each multi-byte I2C read transfer consists of the following:
- START
- Byte 1 = 0xAA
- ACK (generated by the slave)
- Byte 2 = Selected control register address
- ACK (generated by the slave)
- RESTART
- Byte 3 = 0xAB
- ACK (generated by the slave)
- Byte 4-1 = Data byte from the selected control register returned by the FPGA
- ACK (generated by the master)
- Byte 4-2 = Data byte from the selected control register returned by the FPGA
- ACK (generated by the master)
- Byte 4-3 = Data byte from the selected control register returned by the FPGA
- ACK (generated by the master)
- Byte 4-4 = Data byte from the selected control register returned by the FPGA
- NACK (generated by the master)
- STOP
Note: The number of bytes read is not limited to 4 (the 4 bytes read transfer is shown as an example only). As additional bytes are being read, the address pointer is auto-incrementing, starting from the address specified by Byte 2.
5B. Memory Space/Register Definitions
- Table 5-2 Memory Space/Register Definitions
-
Clock_Divider[8:0] Odd/Even Clock Rate (KHz) Actual Pixel Rate (KHz) Decimal Binary 511
111111111
58.708
7.339
500
111110100
60.000
7.500
200
011001000
150.000
18.750
100
001100100
300.000
37.500
67
001000011
447.761
55.970
50
000110010
600.000
75.000
40
000101000
750.000
93.750
37
000100101
789.474
98.684
38
000100110
810.811
101.351
33
000100001
909.091
113.636
29
000011101
1034.483
129.310
25
000011001
1200.000
150.000
22
000010110
1363.636
170.455
20
000010100
1500.000
187.500
18
000010010
1666.667
208.333
17
000010001
1764.706
220.588
15
000001111
2000.000
250.000
14
000001110
2142.857
267.857
13
000001101
2307.692
288.462
12
000001100
2500.000
312.500
11
000001011
2727.273
340.909
10
000001010
3000.000
375.000
8
000001000
3750.000
468.750
7
000000111
4285.714
535.714
1
000000001
30000.000
3750.000
Clock Divider
Odd/Even Clock rate is derived from 60MHz clock as follows:
Odd/Even Clock Rate = 60MHz ÷ (2×Clock_Divider)
The table above provides some examples of the clock divider settings. All values of Clock_Divider[8:0] in the range from 1 to 511 are valid, resulting in the achievable pixel clock in the range from 7.339KHz to 3.750MHz, and the corresponding Odd/Even Clock Rate in the range from 58.708KHz to 30.000MHz. Note: Selecting a clock divider value outside of the valid range will result in the value being ignored. The maximum operation frequency of the sensor is specified as 4MHz.
Integration Time
Integration time is derived based on Odd/Even Clock Rate and the Integration_Time value as follows:
Actual Integration Time = Integration_Time ÷ Odd/Even Clock Rate
Setting Integration_Time[31:0] to 0x00000008 with Clock_Divider[8:0] = 51110 results in integration time being:
8 / 58.708KHz = 136.266µsec
Max Integration Time
Setting Integration_Time[31:0] to 0xFFFFFFFF and Clock_Divider[8:0] = 1 results in integration time being:
(232-1) / 30.000MHz = 143.166sec
Min Integration Time
Setting Integration_Time[31:0] to 0x00000001 and Clock_Divider[8:0] = 51110 results in integration time being:
1 / 58.708KHz = 136.267µsec
- Confirmation
-
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