InGaAs linear sensor reference circuit design - Section 7

John Gilmore, Lu Cheng, Hamamatsu Corporation
Scott Hunt, Analog Devices, Inc.
December 15, 2018

This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.

Section 7: USB Sub-System

The USB interface sub-system is based upon Cypress EZ-USB FX3 development kit. At the heart of the Cypress platform is USB microprocessor CYUSB301X supporting USB3.0 interface.

The USB microprocessor design is based on Cypress Synchronous Slave FIFO. SlaveFIFOSync project is provided as a part of this system. The project is comprised of the following files:

1. cyfx_gcc_startup.S:
Start-up code for the ARM-9 core on the FX3 device. This assembly source file follows the syntax for the GNU assembler.

2. cyfxslfifosync.h:
C header file that defines constants used by this example implementation. Can be modified to select USB connection speed, endpoint numbers and properties, etc.

3. cyfxslfifousbdscr.c:
C source file that contains USB descriptors used by this example. VID and PID are defined in this file.

4. cyfxgpif_syncsf.h:
C header file that contains the data required to configure the GPIF interface to implement the Sync Slave FIFO protocol.

5. cyfxtx.c:
C source file that provides ThreadX RTOS wrapper functions and other utilities required by the FX3 firmware library.

6. cyfxslfifosync.c:
Main C source file.

7. makefile:
GNU make compliant build script for compiling this project.

This project configures and uses the GPIF II interface on the FX3 device in synchronous slave FIFO mode. The FPGA acts as a master device that implements the Cypress-defined Sync Slave FIFO.

This project implements the following functions:
1. Configuration of the GPIF II interface to implement the Sync Slave FIFO protocol.
2. Enumeration as a vendor specific USB device with two bulk endpoints (1-OUT and 1-IN).
3. Creation of MANUAL DMA channels to enable the following data paths:
a. All data received from the USB host through the 1-OUT endpoint is forwarded to the master device on the slave port through socket 3.
b. All data received from the master device on the slave port through socket 0 is forwarded to the USB host through the 1-IN endpoint.
4. When any data packet is received through one of the ingress sockets, the application is notified and forwards the data to the recipient through a DMA callback function.

The output of the compilation is SlaveFifoSync.img, which is loaded into the Cypress EZ-USB board using USB Control Center Application, part of EZ-USB FX3 SDK Software tools.

To load the file into the target perform the following steps (1-5):
1) Connect EZ-USB FX3 board to the PC.
2) Once the drivers for the USB device are installed, the screen shown in Figure 7-1 will be seen.

Figure 7-1: USB control center initial screen

3) Select the device (Cypress FX3 USB BootLoader Device), then click on Program -> FX3 -> RAM (refer to Figure 7-2).

Figure 7-2: Program FX3 device

4) Navigate to the location of "SlaveFifoSync.img" and select "Open."
5) The new driver will be loaded by the operating system, resulting in the following screen shown in Figure 7-3.

Figure 7-3: FX3 device has been programmed

Now, the USB development board is ready to perform data transfers.

Notes

1) The firmware has been loaded into RAM; hence should the power to the board be turned off (or USB cable unplugged from the PC), the programming steps would have to be repeated.
2) It is important to use a high quality USB 3.0 cable and a corresponding USB 3.0 port on the PC.

InGaAs linear sensor reference circuit design - Section 7

Section 7: USB Sub-System

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