InGaAs linear sensor reference circuit design - Section 5

This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.

Section 5: FPGA/USB Processor Control/Status Path

Table 5-1 Control Path I/O Configuration

CYUSB3014-BZX Pin

Synchronous Slave FIFO Interface with 16-bit Data Bus

Interconnect Board
Net Name

FPGA Pin

EZ-USB PWB
I/O Voltage

Description

Name

Location

Control/Status Path

I2C_GPIO[58] D9 I2C_SCL USB_SCL L13 VIO5 SCL line of the I2C control bus
Note: Jumper on interconnect board from
J3.88 to J2.132 needed
I2C_GPIO[59] D10 I2C_SDA USB_SDA M14 VIO5 SDA line of the I2C control bus
Note: Jumper on interconnect board from
J3.86 to J2.134 needed

5A. Access Protocol

  1. The FPGA acts as I2C slave with address 0xAA.
  2. EZ-USB FX3 processor acts as an I2C master.
  3. Each I2C write transfer consists of the following:
    1. START (generated by master)
    2. Byte 1 = 0xAA
    3. ACK (generated by the slave)
    4. Byte 2 = Selected control register address
    5. ACK (generated by the slave)
    6. Byte 3 = Data byte to be written to the selected FPGA control register address
    7. ACK (generated by the slave)
    8. STOP
  4. Each single byte I2C read transfer consists of the following:
    1. START
    2. Byte 1 = 0xAA
    3. ACK (generated by the slave)
    4. Byte 2 = Selected control register address
    5. ACK (generated by the slave)
    6. RESTART
    7. Byte 3 = 0xAB
    8. ACK (generated by the slave)
    9. Byte 4 = Data byte from the selected control register returned by the FPGA
    10. NACK (generated by the master)
    11. STOP
  5. Each multi-byte I2C read transfer consists of the following:
    1. START
    2. Byte 1 = 0xAA
    3. ACK (generated by the slave)
    4. Byte 2 = Selected control register address
    5. ACK (generated by the slave)
    6. RESTART
    7. Byte 3 = 0xAB
    8. ACK (generated by the slave)
    9. Byte 4-1 = Data byte from the selected control register returned by the FPGA
    10. ACK (generated by the master)
    11. Byte 4-2 = Data byte from the selected control register returned by the FPGA
    12. ACK (generated by the master)
    13. Byte 4-3 = Data byte from the selected control register returned by the FPGA
    14. ACK (generated by the master)
    15. Byte 4-4 = Data byte from the selected control register returned by the FPGA
    16. NACK (generated by the master)
    17. STOP

Note: The number of bytes read is not limited to 4 (the 4 bytes read transfer is shown as an example only). As additional bytes are being read, the address pointer is auto-incrementing, starting from the address specified by Byte 2.

5B. Memory Space/Register Definitions

Table 5-2 Memory Space/Register Definitions
Address Name Access Default Bit/Field Register Name/Field Description
0x00 Reg_00 R/O - FPGA F/W Revision
0x01 Reg_01 R/W 0xC0 Mode Control Register
0 Pixel Mode:
0 = 256-pixel mode
1 = 512-pixel mode
1 Interface Speed:
0 = Normal-speed operating mode
1 = High-speed operating mode
2 Interface Style:
0 = Sequential operating mode
1 = Parallel operating mode
Note: When parallel operating mode is enabled, Normal-speed mode is forced regardless of bit 1 setting.
3 Mux Control:
0 = Not inverted
1 = Inverted
4 Gain Control
0: CF_SELECT pin of the array is driven Low (Low Gain)
1: CF_SELECT pin of the array is driven High (High Gain)
5

Reserved
6 Synchronous Slave FIFO Interface Control:
0: Slave FIFO Interface is inactive (only PCLK is active)
1: Slave FIFO Interface is active – data is being transferred
7 Sensor Control:
0: Sensor control is inactive – no pixel data is being acquired
1: Sensor control is active, pixel data is being acquired
0x02 Reg_02 R/W 0x0A Pixel Clock Control Low
7:0 Clock_Divider[7:0]
0x03 Reg_03 R/W 0x00 Pixel Clock Control High
0 Clock_Divider[8]
Note: Writing to Reg_0x03 sets the Clock_Divider[9:0] to the values of registers Reg_02 and Reg_03.
Writing to Reg_02 alone does not change the value of the Clock_Divider[8:0].

Clock_Divider[8:0] is used to set the internal FPGA clock enable used to generate odd and even clocks. The relationship between the divider value and the odd/even clocks is:
60MHz/(2 x Clock_Divider).
The Clock_Divider[8:0] valid values are in the range from 1 to 511. Refer to Table 5-3 for select clock divider settings.
7:1 Reserved
0x04 Reg_04 R/W 0x39 Integration Time Byte 0
7:0 Integration_Time[7:0]
0x05 Reg_05 R/W 0x03 Integration Time Byte 1
7:0

Integration_Time[15:8]
0x06 Reg_06 R/W 0x00 Integration Time Byte 2
7:0 Integration_Time[23:16]
0x07 Reg_07 R/W 0x00 Integration Time Byte 3
7:0 Integration_Time[31:24]
Note: Writing to Reg_0x07 sets the Integration_Time[31:0] to the values of registers Reg_07, Reg_06, Reg_05 and Reg_04.
Writing to Reg_05, Reg_06 or Reg_07 alone does not change the value of the Integration_Time[31:0].
The units are periods of Odd/Even Clock Rate in accordance with Table 5-3.
0x08 Reg_08 R/W 0xD1 AD5235 Digital Potentiometer 1 Low write data
7:0 Digital_Pot1[7:0]
0x09 Reg_09 R/W 0x00 AD5235 Digital Potentiometer 1 High write data
1:0 Digital_Pot1[9:8]
7:2 Reserved
0x0A Reg_0A R/W 0xD9 AD5235 Digital Potentiometer 2 Low write data
7:0 Digital_Pot2[7:0]
0x0B Reg_0B R/W 0x00 AD5235 Digital Potentiometer 2 High write data
1:0 Digital_Pot2[9:8]
7:2 Reserved
0x0C Reg_0C R/O - AD7991 A/D Ch0 Low
7:0 ADC_Ch0[7:0]
0x0D Reg_0D R/O - AD7991 A/D Ch0 High
3:0 ADC_Ch0[11:8]
7:4 Reserved
0x0E Reg_0E R/O - 3:0 AD7991 A/D Ch1 Low
7:0 ADC_Ch1[7:0]
0x0F Reg_0F R/O - AD7991 A/D Ch1 High
- 3:0 ADC_Ch1[11:8]
- 7:4 Reserved
0x10 Reg_10 R/O - AD7991 A/D Ch2 Low
7:0 ADC_Ch2[7:0]
0x11 Reg_11 R/O - AD7991 A/D Ch2 High
3:0 ADC_Ch2[11:8]
4:2 Reserved
0x12 Reg_12 R/W 0x00 Pattern Generator Control
0 1 = Pattern Generator Enable
0 = Pattern Generator Disable
7:1 Reserved
0x13 Reg_13 R/W 0x03 Slave FIFO Control Register
3:0 The number of 16-bit words output to the USB processor following the falling edge of FLAGB.
The number of words resultant = 1 + the value of this field.
7:4 Reserved
0x14 Reg_14 R/W 0x5A AD5627 DAC Low
7:0 DAC[7:0]
0x15 Reg_15 R/W 0x04 AD5627 DAC High
3:0 DAC[11:8]
7:4 Reserved
0x16 Reg_16 R/O - AD5235 Digital Potentiometer 1 Low read data
7:0 Digital_Pot1_Read[7:0]
0x17 Reg_17 R/O -

AD5235 Digital Potentiometer 1 High read data
1:0 Digital_Pot1_Read[9:8]
7:2 Reserved
0x18 Reg_18 R/O - AD5235 Digital Potentiometer 2 Low read data
7:0 Digital_Pot2_Read[7:0]
0x19 Reg_19 R/O - AD5235 Digital Potentiometer 2 High read data
1:0 Digital_Pot2_Read[9:8]
7:2 Reserved
0x1A-0xFF Reserved
Table 5-3 Select Clock Divider Settings
Clock_Divider[8:0] Odd/Even Clock Rate (KHz) Actual Pixel Rate (KHz)
Decimal Binary

511

111111111

58.708

7.339

500

111110100

60.000

7.500

200

011001000

150.000

18.750

100

001100100

300.000

37.500

67

001000011

447.761

55.970

50

000110010

600.000

75.000

40

000101000

750.000

93.750

37

000100101

789.474

98.684

38

000100110

810.811

101.351

33

000100001

909.091

113.636

29

000011101

1034.483

129.310

25

000011001

1200.000

150.000

22

000010110

1363.636

170.455

20

000010100

1500.000

187.500

18

000010010

1666.667

208.333

17

000010001

1764.706

220.588

15

000001111

2000.000

250.000

14

000001110

2142.857

267.857

13

000001101

2307.692

288.462

12

000001100

2500.000

312.500

11

000001011

2727.273

340.909

10

000001010

3000.000

375.000

8

000001000

3750.000

468.750

7

000000111

4285.714

535.714

1

000000001

30000.000

3750.000

Clock Divider

Odd/Even Clock rate is derived from 60MHz clock as follows:
Odd/Even Clock Rate = 60MHz ÷ (2×Clock_Divider)

The table above provides some examples of the clock divider settings. All values of Clock_Divider[8:0] in the range from 1 to 511 are valid, resulting in the achievable pixel clock in the range from 7.339KHz to 3.750MHz, and the corresponding Odd/Even Clock Rate in the range from 58.708KHz to 30.000MHz. Note: Selecting a clock divider value outside of the valid range will result in the value being ignored. The maximum operation frequency of the sensor is specified as 4MHz.

Integration Time

Integration time is derived based on Odd/Even Clock Rate and the Integration_Time value as follows:
Actual Integration Time = Integration_Time ÷ Odd/Even Clock Rate

Setting Integration_Time[31:0] to 0x00000008 with Clock_Divider[8:0] = 51110 results in integration time being:
8 / 58.708KHz = 136.266µsec

Max Integration Time

Setting Integration_Time[31:0] to 0xFFFFFFFF and Clock_Divider[8:0] = 1 results in integration time being:
(232-1) / 30.000MHz = 143.166sec

Min Integration Time

Setting Integration_Time[31:0] to 0x00000001 and Clock_Divider[8:0] = 51110 results in integration time being:
1 / 58.708KHz = 136.267µsec

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