InGaAs linear sensor reference circuit design - Section 4

This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.

Section 4: FPGA/USB Processor Data Path

Figure 4-1: FPGA to EZ-USB FX3 interface

The pixel data is transferred between the FPGA and the USB processor using a 16-bit Synchronous Slave FIFO interface operating at 80MHz.

The data stream consists of 16-bit pixel word comprising 256 or 512 pixels per line.

The line-to-line separator consists of 2x 16-bit marker words:
Marker Word 1: 0xAAAA
Marker Word 2: 0x5555

The marker words appear in sequence: Marker Word 1, followed by Marker Word 2. The marker words are intended to serve the function equivalent to V-sync in video frames. Note: There is no equivalent H-syncs as the frame is a single line.

4A. Interface Configuration

Table 4-1 Data Path I/O Configuration

CYUSB3014-BZX Pin

Synchronous Slave FIFO Interface with 16-bit Data Bus

Interconnect Board
Net Name

FPGA Pin

EZ-USB PWB
I/O Voltage

Description

Name

Location

Data Path

GPIO[17] K8 SLCS# CTL0 L1 VIO1 This is the chip select signal for the Slave FIFO interface. It must be asserted to access Slave FIFO.
GPIO[18] K7 SLWR# CTL1 L4 VIO1 This is the write strobe for the Slave FIFO interface. It must be asserted for performing write transfers to Slave FIFO.
GPIO[19] J7

SLOE# CTL2 M2 VIO1 This is the output enable signal. It causes the data bus of the Slave FIFO interface to be driven by FX3. It must be asserted for performing read transfers from Slave FIFO.
GPIO[20] H7

SLRD# CTL3 L3 VIO1 This is the read strobe for the Slave FIFO interface. It must be asserted for performing read transfers from Slave FIFO.
GPIO[21] G7 FLAGA CTL4 L18 VIO1 These are the FLAG outputs from FX3.

The FLAGs indicate the availability of an FX3 socket.

FLAGA is configured as Current_thread_DMA_RDY.

GPIO[22] G6 FLAGB CTL5 L16 VIO1
GPIO[23] K6 FLAGC CTL6 P2 VIO1 FLAGB is configured as Current_thread_DMA_watermark.
GPIO[25] G5 FLAGD CTL8 T3 VIO1
GPIO[24] H8 PKTEND# CTL7 P1 VIO1 This signal is asserted to write a short packet or a zero length packet to Slave FIFO.
GPIO[28] J5 A1 CTL11 G18 VIO1 This is the 2-bit address bus of Slave FIFO.
GPIO[29] H5 A0 CTL12 K18 VIO1
GPIO[0] F10 DQ[0] DQ[0] H6 VIO1 This is the 16-bit data bus of Slave FIFO.
GPIO[1] F9 DQ[1] DQ[1] D3 VIO1
GPIO[2] F7 DQ[2] DQ[2] M5 VIO1
GPIO[3] G10 DQ[3] DQ[3] L6 VIO1
GPIO[4] G9 DQ[4] DQ[4] T1 VIO1
GPIO[5] F8 DQ[5] DQ[5]

M3

VIO1
GPIO[6] H10 DQ[6] DQ[6] N7 VIO1
GPIO[7] H9 DQ[7] DQ[7] T2 VIO1
GPIO[8] J10 DQ[8] DQ[8] N8 VIO1
GPIO[9] J9 DQ[9] DQ[9] H15 VIO1
GPIO[10] K11 DQ[10] DQ[10] J13 VIO1
GPIO[11] L10 DQ[11] DQ[11] H16 VIO1
GPIO[12] K10 DQ[12] DQ[12] N10 VIO1
GPIO[13] K9 DQ[13] DQ[13] N16 VIO1
GPIO[14] J8 DQ[14] DQ[14] N11 VIO1
GPIO[15] G8 DQ[15] DQ[15] N15 VIO1
GPIO[16] J6 PCLK HSMC_CLKOUT_p2 U18 VIO1 Slave Interface clock 80 MHz.
Note: Jumper on interconnect board from J3.44 to J2.155 needed

4B. EZ-USB Development Board Configuration

Table 4-2 EZ-USB Development Board Configuration
PWB Reference Designator Configuration (Jumper/Switch Setting)
J40 Open
J42 2-3 shorted
J45 2-3 shorted
J47 Open
J50 Open
J52 2-3 shorted
J53 1-3 shorted
J72 1-2 shorted
J74 Open
J98 Open
J97 2-3 shorted
J96 2-3 shorted
J100 1-2 shorted
J101 2-3 shorted
J102 2-3 shorted
J104 1-2 shorted
J103 1-2 shorted
J125 1-2 shorted
J134 3-6 shorted
J135 2-4 shorted
J136 2-5 shorted
J143 2-5 shorted
J144 2-5 shorted
J145 2-5 shorted
J146 2-5 shorted
J156 Open
SW25 1 = OFF
2 = OFF
3 = ON
4 = ON
SW40 1 = ON
2 = ON
3 = ON
4 = ON
Figure 4-2: Cypress EZ-USB development board configuration

4C. FPGA/USB Processor Interface

The USB processor configures the FPGA control registers via I2C interface as described in Section 5. Once the desired configuration parameters have been set, the USB processor sets Reg_01 bits (7:6) = “11”, enabling the sensor control and the Slave FIFO operation.

The USB processor can disable the sensor control and/or Slave FIFO operation at any time in order to re-configure the control registers.

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