InGaAs linear sensor reference circuit design - Section 3

This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.

Section 3: Analog Devices Sensor Board

3A. Theory of Operation and I2C and SPI Device Descriptions

Developed by Analog Devices, Inc. in collaboration with Hamamatsu, this board includes a Hamamatsu G920x InGaAs array, followed by two buffer amplifiers, a multiplexer to select a voltage from one of these two amplifiers, and a 1MSPS SAR ADC with integrated ADC driver. The board also includes a TEC controller and all of the required power conditioning to power the board from an AC adapter. The product selections were chosen to exceed the performance targets of the solution and provide high integration to enable a small footprint and simplicity of design. For more information about the devices chosen for use in this design, please refer to

Although the board does not conform to ANSI/VITA FMC standards due to the form factor and AC adapter power input, the connector area is designed to be able to interface with most FMC-compliant FPGA development boards in order to provide increased flexibility of target platform.

3B. Providing Power to the Board

Provide 9VDC, 1.5A or greater through barrel connector J2 (recommended: CUI, Inc. SMI24-9-V-P5 or similar). Although there is reverse power protection on the board, ensure that the polarity of the AC adapter is center positive for proper operation. For alternative InGaAs array variants, consider the power required by the TEC and ensure enough power is provided. This reference design board can support up to 3A maximum TEC current at up to 5V. A 9V, 2A AC adapter is enough to support a full 3A TEC current due to the high-efficiency 9V to 5V step-down buck regulator (the LTM8053) that is on the board. The power input features reverse protection, a 6A slow-blow fuse, and a 15V bidirectional TVS to protect the board from power supply transients. When using one of the G920x variants which has a 5V, 1.8A TEC, total power draw from the 9V AC wall adapter can be roughly 1.2A at maximum TEC drive.

3C. Array and Buffers

Figure 3-1: Sensor and buffers

Depending on the variant, the array has up to two analog outputs, called ‘Video-even’ and ‘Video-odd’, which are suggested to be buffered in the array datasheet. For the 512-pixel versions of the array, the even pixels come out on one line while the odd pixels are shifted out on the other line. The amplifier and filters are chosen to settle faster than the array, which specifies a 600ns output settling time. Provisions are included to match input resistances for the amplifier by placing 499Ω at R62 and R63 to reduce DC errors due to input bias current. If the 499Ω R62 and R63 are installed, it may be necessary to install C37 and C38 to neutralize the resulting input pole and avoid instability. The analog output of the array can go from 0.76V to 4.5V.

3D. Even-Odd Switch

Figure 3-2: Even-odd multiplexer

A single-pole dual throw (SPDT) solid-state switch follows the even and odd pixel buffer amplifiers and connects one of the two to the ADC. A default pull-up resistor sets the switch to odd when floating, which is the correct side for the 256-pixel arrays. A 499Ω resistor ensures stability of the buffers driving the switch capacitance and reduces current spikes during switching.

3E. ADC Driver and ADC

Figure 3-3: ADC

The ADC driver is integrated into the ADAQ7980. By default, this stage is in unity-gain, which provides the optimal settling and does not negatively affect the noise. Provisions and recommendations are included to match the input to the full-scale 0-5V input range of the ADC if desired. The ADAQ7980 ADC is a 16-bit, 1MSPS SAR ADC with an integrated ADC driver, reference buffer, LDO, and necessary passives that is connected to the SPI bus. For more information about this integrated signal chain, refer to The reference voltage is 5V, so one LSB represents 76.3µV.

3F. Serial Devices

There are a total of 4 serial devices on the reference board:


  • One AD5235 dual 25kΩ, 1024-position digital potentiometer
  • One ADAQ7980 16-bit ADC

I2C Bus

  • One AD7991 12-bit ADC
  • One AD5627 12-bit DAC

3G. AD5235 Dual Potentiometer and Bias Divider

Figure 3-4: Dual POT for Vref and INP bias voltages

The programmable bias voltages for the sensor are derived from a voltage divider off of the precision ADR4550 5V voltage reference used for the ADC. Potentiometer 1 controls the INP voltage from approximately 2.5V at maximum code to approximately 5V at minimum code. Potentiometer 2 controls the VREF_SENSOR voltage from approximately 1V at minimum code to approximately 2V at maximum code. When potentiometer 1 is set to its lowest value of 0, the INP voltage is 5V. When INP is set to the maximum value of 1023, the INP voltage is 2.5V. Intermediate values can be calculated according to the following equation:

Equation 1


where D can range from 0 to 1023. Note that although the AD8606 is a ‘rail to rail’ output amplifier, it will only get to about 4.96V, so writing values lower than ‘16’ to the rheostat may not result in the desired output. This should not be a problem because the maximum bias voltage specified in the G920x datasheet is 4.6V. The default value written to this rheostat should be 205d (0xCD) to get 4.5V.

Potentiometer 2 controls the Vref voltage going to the array. When the potentiometer is set to its lowest value of 0, the output on the Vref pin is 1V. When the potentiometer is set to its highest value of 1024, the output on the Vref pin is 2V. Intermediate values can be calculated according to the following equation:

Equation 2


where D can range from 0 to 1023. Vref should be set to a default value of 1.26V by writing 266d to the potentiometer (0x10A).

3H. AD7991 ADC

Note: I2C address: 010 1001

The AD7991 is a 12-bit ADC with a 2.5V reference provided by the ADN8835, so each LSB represents 610μV. Channel 0 is used to measure the amplified and linearized thermistor output from the ADN8835.

The thermistor uses a simple linearization circuit that results in an output of approximately 26.53mV/°C from -10°C to 40°C, with an offset of 0.566V.

To convert from volts to approximate temperature, use the following equation:

Equation 3

Temperature=ADC Output4096·2500mV-566mV·1°C26.53mV

This approximation will result in errors of slightly over 1°C at -10°C and 40°C, and nearly zero error at 15°C. Note that it is possible to write voltages lower than 0.239V, which will result in a lower setpoint temperature. However, the above approximation will result in large errors. For example, the equation above predicts that 0V corresponds to -21.3°C, while the true temperature would be close to -29°C.

Figure 3-5: Thermistor linear approximation error

If higher accuracy conversion is required, use the following equation:

Equation 4

Temperature degrees K=1Tr+ln-Rx-RfbRfbRtop+Vout1.25V-1RrB-1

Temperature = The thermistor temperature in degrees Kelvin
Tr = 298.15K (Temperature at which nominal thermistor resistance is specified)
Rr = 5kΩ (Nominal thermistor resistance at Tr)
B = 3200K (Thermistor constant given in the datasheet)
Rx = 5.11kΩ (R43 in the schematic)
Rtop = 10kΩ (R32 in the schematic)
Rfb = 12kΩ (R31 in the schematic)

Note: Using this equation results in linearity error dominated by the number format precision used, and should be negligible if implemented in floating point on a PC.

Channel 1 is used to measure the linearized thermistor output from the ‘hot’ side of the heatsink. The same equation as above can be used to convert volts to temperature, assuming the same thermistor is used. Note that once again, the approximate equation will lose accuracy above 40°C, and the full equation should be used if higher temperatures are expected. If a different thermistor is used, then the equation will vary depending on the thermistor’s characteristics. For proper operation, the REF_SEL bit in the AD7991’s Configuration Register must be set to ‘1’ (this uses the Vin3/Vref pin as the converter reference).

Figure 3-6: Temperature monitoring ADC


Note: I2C address: 000 1110

The AD5627 DAC controls the temperature setpoint for the TEC controller. To calculate the temperature setpoint based on the output data written, use the following equation:

Equation 5

Temperature Setpoint=DAC Output4096·5000mV-564mV·1°C26.53mV
Figure 3-7: Temperature setting DAC

3J. TEC Controller

The ADN8835, a TEC controller with integrated 3A power FETs, is used to very accurately control the temperature of the image sensor array. The AD5627 sets the temperature setpoint and the AD7991 reads the hot side and cold side thermistor temperatures. The TEC Voltage Limit and Current Limit are set by resistor dividers tailored to the values needed for the G920x family. To change these limits to accommodate a different family of image sensors with different TEC requirements, see Analog Devices UG-951 for suggestions on the resistor value. For more information on thermoelectric cooler control, refer to ADN8835 datasheet. It may also be necessary to adjust the analog PID components and thermistor components in order to accommodate other sensors. The EN/SY pin is pulled up in order to be enabled by default, but the TEC controller can be shut down if this signal is pulled low by the FPGA. This pin can also be used for synchronization, as described below.

Figure 3-8: TEC control

Indicators and Test Points

Ultralow power LEDs are provided to indicate temp good from the ADN8835 (DS4) and power good for all power rails: DS3 indicates POS5V_TEC, DS2 indicates POS7VA, and DS1 indicates POS5VD/POS5VA power good. Surface mount test points are provided for many signals to be probed, especially in the dense TEC control portion of the circuit, along with corresponding ground test points.

Synchronization Feature and LTM8053 Modes

To remove any switching clock intermodulation from the circuit, this design can be fully synchronized. ADN8835 can be synchronized by driving the shutdown signal, BAR_TEC_SD, with a clock between 1.85MHz and 3.25MHz. LTM8053 can also be synchronized by installing a provisional zero ohm resistor in position R35 to connect its SYNC pin to the BAR_TEC_SD signal. This reduces the maximum synchronization clock frequency to 3MHz. The clocks of both of these devices may be synchronized to a clock output from the FPGA that is synchronous with the sensor pixel clock signals, and the ADAQ7980 samples may be taken at integer multiples of the sync clock frequency, eliminating the effect of switching noise on the measurement. For more information, see the notes on the schematic and the ADN8835 and LTM8053 datasheets. The full complement of SYNC/MODE options for LTM8053 are described in the schematic. By default, the ADN8835 and the LTM8053 are both running on their internal clocks and the LTM8053 is in pulse-skip mode.

Figure 3-9: SYNC / mode selection
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