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InGaAs linear sensor reference circuit design - Section 2
John Gilmore, Lu Cheng, Hamamatsu Corporation
Scott Hunt, Analog Devices, Inc.
December 15, 2018
Section 1: Introduction
Section 2: System description
Section 3: Analog devices sensor board
Section 4: FPGA/USB processor data path
Section 5: FPGA/USB processor control/status path
Section 6: FPGA design description
Section 7: USB sub-system
Section 8: PC software and IGAA driver library
Section 9: Test results
This technical note is divided into nine sections. To navigate to any section, use the hyperlinks above.
Section 2: System Description
The system includes four boards: the analog front-end (AFE) sensor board, the FPGA board, the USB board, and the interconnect board. The AFE sensor board was developed by Analog Devices, Inc. in collaboration with Hamamatsu; this board includes a Hamamatsu InGaAs linear array, followed by a 1MSPS SAR ADC with integrated ADC driver. The board also includes a TEC controller and all of the required voltages conditioning to drive the sensor. The FPGA board issues the control signals to the sensor via the Analog Devices AFE sensor board. The interconnect board is a passive device joining the FPGA development board, USB development board and Analog Devices AFE sensor board together. The overall system interconnection is shown in Figure 2-1.
The data returned by the sensor in response to the FPGA control signals is processed through the A/D converter on the Analog Devices AFE sensor board and received by the FPGA board. The FPGA sends the processed data to the USB processor via the EZ-USB FX3® Slave FIFO Interface for subsequent transfer to a PC.
The data stream received from the Analog Devices sensor board consists of 16-bit words, each representing a single pixel value. The system supports two pixel formats: 256-pixel and 512-pixel mode. The pixel data rate is adjustable from 10KHz to 500KHz, resulting in data throughput of 160Kbps~8Mbps.
The FPGA board is controlled by the USB processor (EZ-USB FX3®) via an I2C interface with the processor acting as an I2C master and the FPGA as an I2C slave. The control is accomplished via a set of the R/W control/status registers in the FPGA memory space. Refer to subsequent sections for the details of the control/status register space and the I2C access protocol.
The logic/flow diagram is shown in Figure 2-2.
Figure 2-1: System interconnection
Figure 2-2: Logic/Flow diagram
- Confirmation
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